\section{TSV RC model with temperature consideration}\label{sec:level3}
Although 3D stacking provides numbers of benefits over traditional 2D circuits, 3D exacerbates the thermal problems due to higher power density in smaller footprint. The temperature variation on chip results in TSV electrical characteristic changing. Several works have been done to explore the temperature dependent TSV modeling \cite{Katti2010a, Katti2011, Xie2009}. 

Besides the temperature-dependent TSV modeling in 3D circuits, the corresponding modeling method is needed for 2.5D circuits, when TSVs are built in the interposer. The difference between 3D circuit and 2.5D circuit on thermal dependent modeling is that for 3D circuit, TSVs go through the silicon and connect two dies or even heat sink, so the thermal problem can be alleviate by building the dissipation path to ambient. However, for 2.5D circuits, TSV may not connect to ambient, the thermal dissipation pattern is different. This part of thermal dependent modeling has not been fully studied yet.

Due to the complexity of temperature-dependent TSV modeling, only semi-analytical capacitance model and empirical RC model are proposed in previous work. First, the semi-analytical capacitance model is introduced in this report with detail calculation steps. Then the empirical RC model formulations are given for direct RC value computation.

\subsection{Semi-analytical temperature-dependent capacitance model}
This model is called semi-analytical because the close-form expression is not given, instead, a four-step algorithm is given to calculate the capacitance until the convergence conditions are satisfied. Normally, the behavior of TSV is similar to a MOS capacitor, and the analytical expression for TSV capacitance is derived by solving a 1D Poisson equation in the radial direction in a cylindrical coordinate system. Considering the depletion region, a semi-analytical algorithm for depletion capacitance calculation is proposed \cite{Katti2011}.

The algorithm first identifies the initial maximum depletion radius, assuming neglecting the hole and electron charges. The initial maximum depletion radius can be obtained from the following equation:
\begin{eqnarray}
\lefteqn{\frac{qN_aR_{OX}^2}{4\varepsilon_{Si}} - \frac{qN_aR_{max}^2}{2\varepsilon_{Si}}Ln(R_{OX})} \nonumber\\
&&+\frac{qN_aR_{max}^2}{4\varepsilon_{Si}}(2ln(R_{max})-1 = \psi_s 
\end{eqnarray}
with the assumption that the surface potential $\psi_s$ equals to $2(K_BT/q)ln(N_a/n_i)$. In the equation, $q$ is the electron charge, $N_a$ is the density of ionized acceptors or the doping concentration, $\varepsilon$ is the silicon permittivity, and $\psi(r)$ represents the electrostatic potential with respect to the radius. 

The second step is trying to identify electron-hole densities in the substrate from the potential with the initial depletion radius calculated from previous step. The potential at every point is calculated as follows:
\begin{eqnarray}
\psi (r) = \frac{qN_a r^2}{4\varepsilon_{Si}}-\frac{qN_aR_{max}^2}{2\varepsilon_{Si}}ln(r) \nonumber \\
 +\frac{qN_aR_{max}}{4\varepsilon_{Si}}(2ln(R_{max}-1)
\end{eqnarray}
The value of the potential at distance $r$ is used to compute the hole and electron charge densities in the substrate using $p(r)=p_{Po}exp(-\beta \psi(r))$ and $n(r)=n_{Po}exp(\beta \psi(r))$.

Step three calculates the new maximum depletion radius with consideration of the hole and electron charge densities derived from previous step. The new maximum depletion radius is calculated from the following equation:
\begin{eqnarray}
\frac{q(N_a +p -n)R^2_{OX}}{4 \varepsilon_{Si}}-\frac{q(N_a +p -n)R^2_{max}}{2 \varepsilon}ln(R_{OX}) \nonumber \\
+\frac{q(N_a +p -n R^2_{max})}{4 \varepsilon_{Si}}(2ln(R_{max})-1)=\psi_s
\end{eqnarray}

The last step calculates the depletion capacitance by using equation $C_{dep} = 2\pi \varepsilon_{Si}L_{TSV}/ln(2R_{max}/\phi_{TSV})$. The final depletion capacitance is obtained by continuing these four steps until the new depletion radius approaches the initial maximum depletion radius. The total TSV capacitance can be viewed as the oxide capacitance and depletion capacitance in serial. 

Comparison between the semi-analytical results and the capacitance extracted from measurement shows that the error is within 3\%. When the temperature rises, the TSV capacitance increases due to the reduction of maximum depletion radius. 

\subsection{Empirical temperature-dependent RC model}
Besides the TSV capacitance, resistance also changes with temperature variation. Lumped RC model should be enhanced by considering TSV capacitance and resistance change due to temperature variation \cite{Katti2010a}. However, since lack of close-form expression for temperature-dependent resistance, paper \cite{Katti2010a} built a 2D/3D ring oscillator to measure the model parameters at different temperatures. Thus, an empirical RC model of TSV is proposed. This RC model is similar to the simple signal-transmission line model at DC and low frequencies without inductances. Resistance exists between the two terminals of TSVs and the capacitance is between TSV metal and substrate. 

The empirical expressions of resistance and capacitance that are obtained from the ring oscillator can be given in the followings:
\begin{eqnarray}
R_{TSV}(T) = R_0(1+\alpha(T-T_0)) \\
C_{TSV}(T) = 0.0007T^2 - 0.0333T +44.4
\end{eqnarray}
where $R_0 = 22m\Omega$ at room temperature ($T_0 = 25\grad C$). The capacitance expression is applicable when the temperature is between room temperature and 100\grad C.

The measurement results suggest that with temperature rises, substantial increment in TSV capacitance and resistance can be seen. However, even at higher temperatures, TSV capacitance is still reduced due to the silicon substrate depletion region. 

The temperature-dependent RLC model is still far beyond mature in nowadays research. However, from these works, we can see that the resistance and capacitance have great dependency on temperatures. Moreover, these dependencies can be translated into factors that further influence the on-chip temperature by producing the Joule heating \cite{Xie2009}. Accurate modeling and electrical-thermal co-analysis framework are required for precise circuit performance and on-chip temperature estimation.